Reducing test data volume using external/LBIST hybrid test patterns

A common approach for large industrial designs is to use logic built-in self-test (LBIST) followed by test data from an external tester. Because the fault coverage with LBIST alone is not sufficient, there is a need to top-up the fault coverage with additional deterministic test patterns from an external tester. This paper proposes a technique of combining LBIST and deterministic ATPG to form “hybrid test patterns” which merge pseudorandom and deterministic test data. Experiments have been done on the Motorola PowerPC microprocessor core to study the proposed hybrid test patterns. Hybrid test patterns provide several advantages: 1) can be applied using STUMPS architecture [Bardell 82] with a minor modification, 2) significantly reduce external test data stored in tester memory, 3) reduce the number of pseudo-random patterns by orders of magnitude, thus addressing power issues.